A prior art device for sequential readout of a memory will now be described with reference to the block diagram of FIG. 1. A memory 10 comprising memory cells and address circuits for these cells is read sequentially from one address to the next using a counter 12 whose value, which corresponds to the address of the cell being read, is incremented by one unit each time an INC signal occurs.
The start of the count address is given by a shift register 14 which contains, in addition to the start address in portion 16, the code of the instruction in portion 18. The shift register 14 is loaded by a microcontroller 20, external to the memory, at the rate of the clock pulses CK which are applied to the shift register 14 and to an AND logic gate 22.
An overflow detector 24 for the shift register 14 supplies a signal for opening the AND logic gate 22 as soon as successive shifts lead to a start of the emptying of the register contents. Further to this opening, the clock pulses CK are applied to a divide-by-N divider circuit 26, where N is the number of bits of a word contained in a memory address, e.g., N=8 or 16 or 24.
The contents of counter 12 are thus incremented by one unit each time the divider has counted N pulses of the clock, and thus selects the next address. The binary digits of a word at the address selected by the counter 12 are read in succession and are stored in an output shift register 28 at the rate of the clock pulses CK. The binary digits are then sent to the microcontroller 20.
The above description shows that the memory 10 is read sequentially line by line with the counter 12 being incremented by the INC signal appearing at every N pulses of the clock. Each clock pulse corresponds to the readout of a digit forming the binary word contained at the address Ad given by the counter 12.
When the readout is to be carried out with a jump to a new address, the microcontroller must send a new message that contains a jump instruction and a new address. It is thus necessary for the microcontroller 20 to send a complete message, which takes time and reduces the average speed of the operations in a program. This problem is enhanced as the program contains many address jumps.